1. Field of the Invention
The invention relates to integrated circuits. An object of the invention is a non-volatile electrically programmable bistable multivibrator. It is designed essentially, though not exclusively, for use in a redundancy circuit of a memory in integrated circuit form.
2. Discussion of the Related Art
To provide for a clear understanding of the invention in the context in which it has been conceived, a brief reminder shall first of all be given of the principles of redundancy circuits currently used in large-capacity memories.
The redundancy circuits of a memory are implemented when defects appear in the rows (word lines used to address the memory) or the columns (bit lines conveying the data elements to be read or written in the memory).
For example, if a column is defective, it is replaced by a redundancy column as follows: the address of the defective column is memorized in a defective address memory; this defective address memory is a memory of the type that is addressable by its contents (hereinafter called CAM or contents addressable memory); whenever an address is applied to the main memory, this address is also applied to the CAM. If the address applied is identical to the address memorized, a redundancy circuit is put into operation and acts to disconnect the defective column and to connect a redundant column in its place in a way that is invisible to the user.
In practice, according to the organization of the main memory, if a column is defective, it is rather a group of columns containing this defective column that will be replaced by a group of redundancy columns: in general, if a group of columns is defined by an address bit of the large-capacity memory, it is this group of columns that will be replaced as a whole. Hereinafter, for simplicity's sake, reference shall be made, in the description, to the replacing of only one column rather than to the replacing of a group of columns.
For a main memory of several megabits, the possibility of repairing several defects is foreseen. There are therefore as many redundancy columns as there are defective columns or rows which it should be possible to repair. With each redundancy column, there is associated a respective CAM containing the address of a defective column. If N defects are to be repaired, N redundancy columns and N CAMs are needed. Typically, N=36 for a four-megabit or sixteen-megabit memory.
If a column of the main memory is designated by an M-bit address (for example M=5), then each CAM contains at least M+1 bits: M bits to define the address of a defective column and one validation bit to indicate that the redundancy circuit corresponding to this CAM should actually be activated when the defective address is applied to the CAM.
To make CAMs, the first devices used were groups of physical fuses, fused electrically or fused by laser beam, each fuse representing an address bit or a validation bit. These fuses had drawbacks (relating to reliability, bulkiness, consumption, and difficulty of programming) and were soon replaced by non-erasable non-volatile memory cells. The latter too had drawbacks (they consumed substantial current) and there was a gradual trend towards the use of programmable bistable multivibrators comprising two floating-gate transistors for each address bit or validation bit.
FIG. 1 shows a prior art non-volatile programmable bistable multivibrator constituting a storage cell of a defective address bit (or a validation bit), and therefore constituting one of the M-1 cells of a defective address CAM.
The output OUT of this cell is at a logic level 0 or 1 depending on the state in which the bistable multivibrator is programmed. This output therefore defines a value of an address bit (or the value of the validation bit).
If the cell corresponds to one of the M defective address bits, the output of each cell of these M address bits is applied to an input of an exclusive-0R gate (not shown). The exclusive-OR gate receives, at another input, a corresponding address bit received by the main memory. The outputs of the exclusive-OR gates corresponding to the different address bits of one and the same defective address memory are applied to an input of a NOR gate (not shown). The output of this NOR gate gives a logic 1 level only when there is coincidence between all the address bits applied and all the corresponding bits of the defective address memory. The output of the NOR gate is validated by the output of the memory cell corresponding to the validation bit, for example by means of an AND gate (not shown). The output of the AND gate is the output of the CAM and is used to put a redundancy path into operation whenever the address applied to the main memory corresponds to the defective address recorded.
In general, there are N memories with defective addresses, for example N=36. During the testing of the main memory, the detection of a defective column activates the storage of the address of this column in one of the CAMs. The different CAMs are thus successively programmed as and when the defects are detected. During the normal operation of the main memory, the addresses of this memory are applied simultaneously to all the CAMs. If there is correspondence between the applied address and the address stored in one of them, the redundancy path corresponding to this address is activated.
To enable the programming of a defective address in a CAM, it is therefore provided that a respective address bit of the main memory will be applied to each cell of the CAM. The programming is done upon a command of the testing apparatus in the event of the detection of a defect at the address being tested.
The individual memory cell shown in FIG. 1 has two arms with a floating-gate transistor TGF1, TGF2 in each arm. The arms are arranged so as to form a bistable multivibrator as soon as one of these two transistors is programmed. The state of the bistable multivibrator, represented by the output OUT and corresponding to an address bit or a validation bit, is then a function of that one of the two transistors which is programmed. At the outset, the two transistors are in a non-programmed or blank state. During the testing of the memory, one of the two transistors is programmed to obtain either a 0 or a 1 at the output OUT of the cell, thus defining a definitive stable state 0 or 1 of the cell.
More specifically, the cell of FIG. 1 has two identical arms in parallel between a supply terminal A (potential Vcc of the order of 3 volts) and a terminal B. The terminal B is at a zero potential VS in reading or programming mode and may also be taken to a high potential VS (12 volts) in erasure mode if an erasure mode is planned (flash EPROM). In series in each arm, there is a P channel transistor (T1, T2), an N channel transistor (T3, T4), and a floating-gate transistor (TGF1, TGF2). The gate of the P channel transistor (T1, T2) of one of the arms is connected to the drain of the P channel transistor (T2, T1) of the other arm. The gates of the N channel transistors (T3, T4) are connected together to acommon potential VB whose value depends on the mode ofoperation (about 1.8 volts in reading mode; 0 volts in programming or erasure to have one volt at the drain of the cells in reading mode). The transistors T3 and T4 are insulation transistors in order to prevent the transmission, to the transistors T1 and T2, of the relatively high voltages applied to the floating-gate transistors in programming or erasure mode. The gates of the floating-gate transistors TGF1, TGF2 are connected to a common potential VGF depending on the operation (about 3 volts in read mode, about 12 volts in programming mode). The source of these transistors is connected to the node B (potential VS). The drain potentials of the floating-gate transistors are controlled by transistors T5 and T6 respectively, enabling either the connection of the drain to a programming potential VPRG (transistor T5 or T6 conductive) or the leaving of the drain in high impedance (transistor T5 or T6 off). In programming mode, the gate of the transistor T5 is controlled by a programming signal PROG and the gate of T6 by a complementary signal NPROG. As a result, a choice is made, depending on the state of the signal PROG, of that transistor of the two floating transistors which must be programmed and that transistor which must remain blank. In reading mode, the drain of the transistors T5 and T6 remains in a state of high impedance, the voltage VPRG being not applied to these drains.
The cell is called a bistable cell because it has one stable state among two possible states, the stable state that it takes depending on that one of the two transistors that has been programmed. The state of the cell is readat the drain of one of the P channel transistors (T2 for example). This drain is connected to the input of a first inverter INV1 followed by a second inverter INV2. The output of INV2 is the output OUT of the cell. The output of INV1 is used as a complementary output NOUT if it is needed.
Finally, a supplementary transistor T7 may make it possible, solely in test mode, in order to avoid the floating nodes when T3 and T4 are off, to place the input of the inverter INV1 temporarily at the ground (for an initialization of the state of the cell at each power-on-reset operation). The gate of this transistor is activated by an initializing rectangular-wave signal INIT produced by a standard power-on-reset circuit (not shown).